1. Field of the Invention
The invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices use the optical anisotropy and polarization properties of liquid crystal molecules of a liquid crystal layer to produce an image. The liquid crystal molecules have long, thin shapes, and the liquid crystal molecules can be arranged along a certain direction. The alignment direction of the liquid crystal molecules can be controlled by varying the intensity of an electric field applied to the liquid crystal layer. Accordingly, the alignment of the liquid crystal molecules is changed by the electric field. Light is transmitted and refracted according to the alignment of the liquid crystal molecules to display an image.
A liquid crystal display device includes a color filter substrate having a common electrode, an array substrate having a pixel electrode, and a liquid crystal layer interposed between two substrates. The liquid crystal display device is driven by a vertical electric field induced between the common electrode and the pixel electrode and has superior transmittance and aperture ratio.
The pixel electrode of the array substrate and the common electrode of the color filter substrate form a liquid crystal capacitor. A voltage applied to the liquid crystal capacitor is not maintained until a next signal is provided and is leaked. Accordingly, to maintain the applied voltage, a storage capacitor is connected to the liquid crystal capacitor.
Generally, the storage capacitor can be formed by two methods. One method may be referred to as a storage-on-common or independent storage capacitor type, in which an electrode for the storage capacitor is further formed and is connected to the common electrode. The other method may be referred as a storage-on-gate or previous gate type, in which a part of an (n−1)th gate line is used as an electrode for the storage capacitor of an nth pixel.
The storage-on-gate type has an advantage that an outer storage line is not needed because a signal for the storage capacitor is applied through the gate line. However, the storage-on-gate type has a disadvantage in that there is signal interference due to coupling with a gate signal.
On the other hand, the storage-on-common (SOC) type has an advantage in that there is no signal interference in the gate signal and an enough storage capacitance can be secured. However, a storage line is further formed, and this causes a decrease in the aperture ratio.
A related art SOC type liquid crystal display (LCD) device will be explained with reference to the accompanying drawings.
FIG. 1 is a plan view illustrating an array substrate for an SOC-type LCD device according to the related art.
In FIG. 1, first and second gate lines 20a and 20b and first, second, and third data lines 30a, 30b and 30c are formed on a substrate 10 in a matrix shape. The first, second and third data lines 30a, 30b and 30c cross the first and second gate lines 20a and 20b to define first and second pixel regions P1 and P2. Scan signals are applied to the first and second gate lines 20a and 20b, and data signals are applied to the first, second and third data lines 30a, 30b and 30c. 
First and second common lines 50 and 51 are formed between the first and second gate lines 20a and 20b. Each of the first and second common lines 50 and 51 has an H-like shape.
The first common line 50 includes a horizontal part 50a and first and second vertical parts 50b and 50c. The horizontal part 50a is disposed in the first pixel region P1 along a horizontal direction in the context of the figure. The first and second vertical parts 50b and 50c extend from respective ends of the horizontal part 50a along a vertical direction in the context of the figure. The first and second vertical parts 50b and 50c are parallel with the data lines 30a, 30b and 30c and are adjacent to the first and second data lines 30a and 30b, respectively.
The second common line 51 also includes a horizontal part 51a and first and second vertical parts 51b and 51c. The horizontal part 51a is disposed in the second pixel region P2 along the horizontal direction in the context of the figure. The first and second vertical parts 51b and 51c extend from respective ends of the horizontal part 51a along the vertical direction in the context of the figure. The first and second vertical parts 51b and 51c are parallel with the data lines 30a, 30b and 30c and are adjacent to the second and third data lines 30b and 30c, respectively.
The second vertical part 50c of the first common line 50 is connected to the first vertical part 51b of the second common line 51 through first and second common bridge lines 53 and 54. The first and second common bridge lines 53 and 54 are repeatedly formed between adjacent pixel regions and connect the common lines in adjacent pixel regions. Accordingly, all the common lines on the substrate 10 are electrically connected to one another through the first and second common bridge lines 53 and 54, and a common signal from a common signal generating unit (not shown) is applied to all the common lines on the substrate 10.
A first thin film transistor T1 is formed at a crossing portion of the second gate line 20b and the first data line 30a. A second thin film transistor T2 is formed at a crossing portion of the second gate line 20b and the second data line 30b. 
The first thin film transistor T1 includes a first gate electrode 25a, a first semiconductor layer (not shown), a first source electrode 32a and a first drain electrode 34a. The first gate electrode 25a extends from the second gate line 20b into the first pixel region P1. The first semiconductor layer (not shown) overlaps and is disposed over the first gate electrode 25a. The first source electrode 32a extends from the first data line 30a and is disposed over the first semiconductor layer. The first drain electrode 34a is spaced apart from the first source electrode 32a. 
The second thin film transistor T2 includes a second gate electrode 25b, a second semiconductor layer (not shown), a second source electrode 32b and a second drain electrode 34b. The second gate electrode 25b extends from the second gate line 20b into the second pixel region P2. The second semiconductor layer (not shown) overlaps and is disposed over the second gate electrode 25b. The second source electrode 32b extends from the second data line 30b and is disposed over the second semiconductor layer. The second drain electrode 34b is spaced apart from the second source electrode 32b. 
The first semiconductor layer includes a first active layer 40a of intrinsic amorphous silicon (a-Si:H) and a first ohmic contact layer (not shown) of impurity-doped amorphous silicon (n+ a-Si:H). The second semiconductor layer includes a second active layer 40b of intrinsic amorphous silicon (a-Si:H) and a second ohmic contact layer (not shown) of impurity-doped amorphous silicon (n+ a-Si:H).
First and second contact holes CH1 and CH2 expose the first and second drain electrodes 34a and 34b, respectively.
First and second pixel electrodes 70a and 70b are formed in the first and second pixel regions P1 and P2, respectively. The first pixel electrode 70a contacts the first drain electrode 34a through the first drain contact hole CH1. The second pixel electrode 70b contacts the second drain contact hole 34b through the second drain contact hole CH2. The first and second pixel electrodes 70a and 70b are formed of one selected from a transparent conductive material group including indium tin oxide (ITO) and indium zinc oxide (IZO).
A cross-sectional structure of an array substrate for an SOC-type LCD device according to the related art will be explained with reference to the accompanying drawings.
FIG. 2 is a cross-sectional view taken along the line II-II′ of FIG. 1.
In FIG. 2, the first and second pixel regions P1 and P2, a first switching region S1, first and second common regions C1 and C2, and a second data region D2 are defined on the substrate 10.
The first gate electrode 25a extending from the second gate line 20b of FIG. 1 is formed on the substrate 20 including the regions P1, P2, S1, C1, C2 and D2. In addition, the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51 are formed in the first and second common regions C1 and C2, respectively. The second common bridge line 54 is formed between the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51. The second common bridge line 54 electrically connects the second vertical part 50c of the first common line 50 to the first vertical part 51b of the second common line 51.
A gate insulating layer 45 is formed on the first gate electrode 25a, the second vertical part 50c of the first common line 50, the first vertical part 51b of the second common line 51 and the second common bridge line 54. The gate insulating layer 45 is formed of one selected from an inorganic insulating material group including silicon oxide (SiO2) and silicon nitride (SiNX).
The first active layer 40a of intrinsic amorphous silicon and the first ohmic contact layer 41a of impurity-doped amorphous silicon are sequentially formed on the gate insulating layer 45 overlapping the first gate electrode 25a. The first active layer 40a and the first ohmic contact layer 41a have an island shape and constitute the first semiconductor layer 42a. 
The first source electrode 32a and the first drain electrode 34a are formed on the first semiconductor layer 42a. The first source electrode 32a extends from the first data line 30a of FIG. 1. The first drain electrode 34a is spaced apart from the first source electrode 32a. In addition, the second data line 30b is formed in the second data region D2 and overlaps the second common bridge line 54.
A passivation layer 55 is formed on the first source electrode 32a, the first drain electrode 34a and the second data line 30b. The passivation layer 55 has the first drain contact hole CH1 exposing the first drain electrode 34a. 
The first pixel electrode 70a and the second pixel electrode 70b are formed on the passivation layer 55. The first pixel electrode 70a is disposed in the first pixel region P1 and is connected to the first drain electrode 34a through the first drain contact hole CH1. The second pixel electrode 70b is disposed in the second pixel region P2 and is connected to the second drain electrode 34b of FIG. 1 through the second drain contact hole CH2 of FIG. 1.
Here, the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51 are disposed to be as close to the second data line 30b as possible, and the second common bridge line 54 connects the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51. The first pixel electrode 70a partially overlaps the first vertical part 50b of FIG. 1 and the second vertical part 50c of the first common line 50, and the second pixel electrode 70b partially overlaps the first vertical part 51b and the second vertical part 51c of FIG. 1 of the second common line 51.
However, in the above-mentioned array substrate, there is a limitation on increasing the aperture ratio.
FIG. 3 is a cross-sectional view of an SOC-type LCD device according to the related art and corresponds to a cross-section taken along the line III-III′ of FIG. 1.
In FIG. 3, a color filter substrate 5 and an array substrate 10 are facing each other and attached with a cell gap g therebetween. Each of the color filter substrate 5 and the array substrate 10 includes a display area AA and a non-display area NAA. A liquid crystal layer 15 is interposed between the color filter substrate 5 and the array substrate 10. The liquid crystal layer 15 has a thickness corresponding to the cell gap g. The color filter substrate 5, the array substrate 10 and the liquid crystal layer 15 constitute a liquid crystal panel 30. A backlight unit 90 is disposed at a rear surface of the array substrate 10 as a light source.
Even though not shown in the figure, a seal pattern is formed between the color filter substrate 5 and the array substrate 10 along peripheries. The seal pattern may be formed of a thermosetting resin.
The color filter substrate 5 includes a transparent substrate 1, a black matrix 12, a color filter layer 16, an overcoat layer 14 and a common electrode 80. The black matrix 12 is formed at a lower surface of the transparent substrate 1 and blocks light incident on the non-display area NAA. The color filter layer 16 is formed on the black matrix 12 and includes a red sub color filter 16a, a green sub color filter 16b and a blue sub color filter (not shown) that are subsequently patterned. The overcoat layer 14 is formed on the color filter layer 16. The common electrode 80 is formed on the overcoat layer 14 and is formed of a transparent conductive material.
The array substrate 10 includes a transparent substrate 2, the second vertical part 50c of the first common line, the first vertical part 51b of the second common line 51, the gate insulating layer 45, the second data line 30b, the passivation layer 55, and the first and second pixel electrodes 70a and 70b. The second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51 are formed on an upper surface of the transparent substrate 2 and are spaced apart from each other such that the second data region D2 is disposed therebetween. The gate insulating layer 45 covers the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51. The second data line 30b is disposed in the second data line D2 on the gate insulating layer 45. The passivation layer 55 covers the second data line 30b. The first and second pixel electrodes 70a and 70b are formed on the passivation layer 55 in the first and second pixel regions P1 and P2, respectively, such that the second data line 30b is disposed therebetween.
In the SOC-type LCD device, since the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51 are formed under the second data line 30b, there is no poor image problem such as crosstalk, which is caused by a change of a data signal due to a parasitic capacitance between the first and second pixel electrodes 70a and 70b and the second data line 30b, even if the first and second pixel electrodes 70a and 70b are close to the second data line 30b. However, the aperture ratio is lowered because the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51 are spaced apart from each other.
Moreover, the black matrix 12, which is disposed in the non-display area NAA on the lower surface of the transparent substrate 1 of the color filter substrate 5, is designed with an attachment margin of about 2 □m at both ends to cover the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51 by considering an attachment error when the color filter substrate 5 and the array substrate 10 are attached. Accordingly, the aperture ratio is further reduced by the attachment margin.
Furthermore, in the SOC-type LCD device having a small size, for example, less than 10 inches, attempts for reducing costs have been made by increasing the aperture ratio of the liquid crystal panel 30 and removing optical sheets of the backlight 90.
However, the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51 are spaced apart from each other at both sides of the second data line 30b and are connected to each other through the first and second common bridge lines 53 and 54 of FIG. 1 overlapping the second data line 30b. It is restricted to decrease a distance between the second vertical part 50c of the first common line 50 and the first vertical part 51b of the second common line 51 because of a limitation in a resolution of a light-exposing apparatus. Therefore, it is difficult to increase the aperture ratio.
Accordingly, the prevention invention is directed to an array substrate for a liquid crystal display device and method of manufacturing the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.